Logic Gates, Part 3: Building a Processor

Part 1 ended with an ALU that computes, part 2 with registers that remember and state machines that step through a sequence. That is all a processor is made of. This part puts the pieces together into a small processor for a subset of RISC-V, a real and open instruction set. On the way you will turn bits into instructions, write your first programs in assembly and watch the processor run them, wire by wire.

From state machine to processor

A processor is a state machine too. Its state is the program counter (PC), which holds the address of the next instruction, plus the registers and the memory. What makes it more than a traffic light is where its next step comes from: the instructions are stored in memory as numbers, just like data. Patterson and Hennessy name these two principles, instructions represented as numbers and programs stored in memory like data, as the basis of the stored-program computer [1].

Which instructions a processor understands, how they are encoded and what they do is laid down in its instruction set architecture (ISA). Hennessy and Patterson describe the ISA as the boundary between software and hardware [2]: a program written for it runs on every processor that implements it, however that processor is built inside. This article uses RISC-V, whose specification is open and free to read [3]. Its base instruction set for 32 bits, RV32I, has 32 registers of 32 bits each, x0 to x31, and x0 always reads as 0 [3]. We take ten instructions from it: add, sub, and, or, addi, lw, sw, beq, bne and blt. Patterson and Hennessy build their simple processor for almost the same set, in the 64-bit variant with the loads and stores ld and sd [1].

An instruction is a number

Every RISC-V instruction is 32 bits long and divided into fields [3]. The opcode in the lowest seven bits says what kind of instruction it is. Other fields name registers, or hold an immediate: a constant that is part of the instruction itself. Our subset uses four formats: R-type for operations on two registers, I-type for operations with an immediate and for loads, S-type for stores and B-type for branches. The source registers rs1 and rs2 and the destination register rd sit in the same bits in every format, which keeps decoding simple [3].

Click through the bits of an instruction. Whenever the pattern is one the processor understands, the line below shows it as text. That line is assembly language.

Assembly: names for the bits

Nobody writes programs as rows of bits. Assembly language gives every instruction a short name and writes its fields as operands: add x3, x1, x2 means x3 = x1 + x2, with the destination first. An assembler translates each line into its 32 bits: one line, one instruction.

Besides the ten instructions, our assembler knows two pseudo-instructions from the specification: nop, which is addi x0, x0, 0 and changes nothing, and mv rd, rs, which is addi rd, rs, 0 and copies a register [3]. To load a constant, add it to x0: addi x5, x0, 10 puts 10 into x5. Immediates have 12 bits and range from −2048 to 2047, in two's complement as in part 1. A label such as loop: names the address of the next instruction; bne x5, x0, loop jumps there if x5 is not 0, and the assembler works out the distance in bytes. The branch adds it to its own address, within ±4 KiB [3].

Memory is addressed in bytes, so its words of four bytes are at the addresses 0, 4, 8 and so on. lw x8, 0(x5) loads the word at address x5 + 0, sw x8, 32(x0) stores x8 at address 32 [3]. The data memory here holds sixteen words; the first five are 2, 3, 5, 7 and 11.

That is all the assembly this article needs. Real programs also call functions, keep data on a stack and talk to the operating system, but for a processor that runs loops, ten instructions are enough. Step through the examples, then solve the challenges with your own code.

The register file

Inside, the processor needs a home for its 32 registers: the register file. An instruction like add reads two registers and writes one, so the register file has two read ports and one write port [1]. Reading is combinational: for each read port, a multiplexer like the one in part 1 picks one of the registers. Writing goes through the clock: a decoder selects the register rd, and only if the control signal RegWrite is 1 does it take the new value at the clock edge, like the registers in part 2 [1].

The datapath, piece by piece

Now the parts can be wired together into a datapath. Patterson and Hennessy build it in steps [1, sec. 4.3]. First the fetch: the PC addresses the instruction memory, and an adder computes PC + 4, the address of the next instruction. The PC with its adder is the counter from part 2. For R-type instructions, two registers go into the ALU and the result goes back into the register file. For loads and stores, the ALU adds a register and the sign-extended immediate to form the address. For branches, the ALU subtracts the two registers, and its Zero flag says whether they are equal; a second adder computes the branch target.

Wherever two sources can feed one input, a multiplexer chooses: the register or the immediate for the ALU (ALUSrc), the ALU result or the memory for the register file (MemtoReg), PC + 4 or the branch target for the PC. Instructions and data have separate memories, because a single-cycle processor reads an instruction and accesses data in the same clock cycle and can use each part only once per instruction [1, sec. 4.3]. For bne and blt we add a small box that checks the condition: Zero for beq, not Zero for bne, and for blt the signed comparison [3], which follows from the flags of part 1 as Negative ≠ Overflow.

Control: who sets the switches

Who sets all these multiplexers and enables? The control unit. It reads the opcode and sets seven signals. In a single-cycle processor it needs no memory at all: every instruction is done in one clock cycle, so the signals follow from the opcode alone, a truth table like the ones in part 1 [1, sec. 4.4]. The ALU is controlled in two levels. The control unit sends a two-bit ALUOp, meaning add, subtract or “look at funct3 and funct7”, and a small ALU control turns it into the control lines of the ALU from part 1 [1, sec. 4.4]. Processors that spread an instruction over several clock cycles need a state machine for their control, as promised in part 2.

Take the place of the control unit: set the signals for each instruction, then check your answer.

Running a program

Put together, this is a complete processor. In every clock cycle the datapath settles to the instruction at the PC; at the clock edge the PC, at most one register and at most one word of memory take their new values. Pick a program and step through it, or write your own. The values on the buses are those of the current clock cycle.

Why one clock cycle is too slow

There is a catch. Every instruction gets one clock cycle, so the clock must be slow enough for the slowest one. Patterson and Hennessy's example assumes 200 ps for a memory access and for the ALU, and 100 ps for reading or writing the register file. A load needs all five steps and takes 800 ps, a branch only 500 ps, yet every instruction is given the full 800 ps [1, sec. 4.6]. Move the slider: the slower the memory, the more time is spent waiting.

The better idea comes from the assembly line. Split every instruction into its five steps, called IF, ID, EX, MEM and WB, and let five instructions work at the same time, each in a different step [1, sec. 4.6]. This is pipelining, and it is the topic of the next part.

Where to go from here

You have now seen every layer of a simple processor, from the switch in part 1 to a program that runs on it. Real processors add much more: multiplication, function calls with a stack, interrupts, caches and, above all, pipelines. Patterson and Hennessy's Computer Organization and Design follows this path in detail [1], Hennessy and Patterson's Computer Architecture: A Quantitative Approach shows how processors are made fast [2], and the full instruction set is in the RISC-V specification [3].

Back to part 1: from a switch to an ALU or part 2: memory and state machines.

References

1. D. A. Patterson and J. L. Hennessy, Computer Organization and Design RISC-V Edition: The Hardware/Software Interface, 2nd ed. Morgan Kaufmann (Elsevier), 2020. ISBN 978-0-12-820331-6. Used here: chapter 2 “Instructions: Language of the Computer”; sections 4.3 “Building a Datapath”, 4.4 “A Simple Implementation Scheme” and 4.6 “An Overview of Pipelining”; appendix A “The Basics of Logic Design.” Publisher's page
2. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 6th ed. Morgan Kaufmann (Elsevier), 2017. ISBN 978-0-12-811905-1. Publisher's page
3. RISC-V International, The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, version 20260120, 2026. Used here: chapter 1 “RV32I Base Integer Instruction Set, Version 2.1.” Online at RISC-V International